Such circuits are well known. It is merely recalled that they are used for locking the phase of a digital "outgoing" signal as provided by said loop to the phase of a digital "incoming" signal received by said loop, and that they operate essentially by incrementing or decrementing the frequency of a clock signal provided by an oscillator internal to said loop, as a function of the phase difference that exists between said incoming and outgoing signals. The signal for controlling incrementing or decrementing the frequency of the clock signal delivered by said oscillator is itself delivered by the "overflow" output of a counter which is triggered by a signal representative of said phase difference, and which counts at the rate of a clock signal that is also delivered by said internal oscillator.
The invention applies particularly to synchronizing a telecommunications terminal that is connected to a telecommunications network operating in asynchronous transfer mode, via an "adaptor" circuit enabling a synchronous interface to be reconstituted relative to said terminal, such an adaptor circuit making use of a digital phase locked loop to generate a clock signal whose mean frequency is equal to the base frequency of said synchronous interface, and whose phase is servo-controlled to the phase of an incoming clock signal at a rate equal to the rate of the data received from said network by said adaptor circuit.
When a call is established involving said terminal, such an application requires simultaneously both a relatively short locking time for said loop and a relatively long filtering time to satisfy the conditions laid down by the standards governing such an interface concerning the maximum jitter acceptable for said clock signal whose mean frequency is equal to the base frequency of said synchronous interface. Such conditions are generally strict.
For such an application in which the input signal for said loop is present intermittently, with arbitrary phase state from one occasion to another, it may be necessary to use a method in which the operating mode of such a loop is controlled to pass through the following steps in order:
detecting the beginning of the presence of said input signal;
selecting a counting range for said counter that is relatively small in value in order to enable said loop to lock relatively quickly;
detecting that said loop has locked; and
selecting a count range for said counter having a relatively large value in order to provide a relatively high degree of filtering on possible phase variations in said input signal that may occur while it is present, with this last setting being retained until the next time a beginning of the presence of said input signal is detected.
An object of the present invention is to provide a circuit enabling such locking to be detected.